1. Technical Field
The present disclosure relates generally to phase locked loops (hereinafter, referred to as ‘PLL’), and more specifically, to a PLL having a controller for dividing values of a voltage controlled oscillator (hereinafter, referred to as ‘VCO’) in all frequency bandwidths.
2. Background
FIG. 1 is a block diagram illustrating a conventional PLL having a program counter.
The PLL comprises a phase comparator 1, a low pass filter LPF 2, a VCO 3 and a program counter 4. The phase comparator 1 compares a reference frequency fr of an external clock signal ECLK with a comparison frequency fp of a comparison clock signal PCLK. The low pass filter LPF 2 filters an output signal from the phase comparator 1. The VOC 3 generates a signal of frequency varying proportional to the DC signal from the low pass filter 2. The program counter 4 divides a frequency of an output clock signal ICLK from the VCO 3 at a predetermined 1/N division ratio.
An output frequency fvco of the output clock signal ICLK from the VCO 3 is divided into 1/N by the program counter 4. The divided frequency negatively feeds back as the comparison frequency fp, and then it is inputted into the phase comparator 1.
Here, the output frequency fvco from the voltage control oscillator 3 is defined by the following equation 1:                     fp        =                  fvco          N                                    Equation        ⁢                                   ⁢        1            
Here, fp=fr, and [Equation 1] can be represented by the following equation 2:fvco=N×fr  Equation 2
Equation 2 shows that if the value of N varies, the output frequency fvco can be changed by the step of the reference frequency fr.
Accordingly, if the output frequency fvco is used in local oscillators of various telecommunication apparatus, one crystal oscillator can use various frequencies with the high stability. However, if the output frequency fvco becomes larger, it is difficult for the program counter 4 to divide the larger output frequency fvco.
Accordingly, a PLL uses a prescaler which can operate at a high speed, as shown in FIG. 2.
FIG. 2 is a block diagram illustrating a conventional PLL having a prescaler.
The PLL comprises a phase comparator 11, a low pass filter 12, a VCO 13, a prescaler 14 and a program counter 15. The phase comparator 11 compares a reference frequency fr of an external clock signal ECLK with a comparison frequency fp of a comparison clock signal PCLK. The low pass filter 12 filters an output signal from the phase comparator 11. The VCO 13 generates a signal of frequency proportional to a DC signal of the low pass filter 12. The prescaler 14 divides an output signal from the VCO 13 into 1/M. The program counter 15 divides a clock signal divided by the prescaler 14 into 1/N.
The output frequency fvco from the VCO 13 is divided into 1/M by the prescaler 14. And the divided output frequency fvco is divided into 1/N by the program counter 15 again. The divided frequency negatively feeds back as the comparison frequency fp, and it is inputted into the phase comparator 11.
Here, the comparison frequency fp is defined by the following equation 3:                     fp        =                  fvco                      N            ×            M                                              Equation        ⁢                                   ⁢        3            
Accordingly, the output frequency fvco is defined by the following equation 4. Here, fp=fr.fvco=N×M×fr  Equation 4
In Equation 4, if the division ratio N of the program counter 15 varies, the output frequency fvco is changed into a step of M×fr. As a result, M×fr is a channel separation, which is a frequency interval of channel. And the reference frequency fr in a synthesizer is division ratio 1/M of the channel separation.
FIG. 3 is a block diagram illustrating a conventional PLL having a swallow counter setting a channel separation as the reference frequency fr.
The PLL comprises a phase comparator 21, a low pass filter 22, a VCO 23, a dual modulus prescaler 24, a program counter 25, a swallow counter 26 and a controller 27. The phase comparator 21 compares the reference frequency fr with the comparison frequency fp. The VCO 23 generates a signal of frequency proportional to a DC signal from the low pass filter 22. The dual modulus prescaler 24 divides a frequency of an output clock signal ICLK from the VCO 23 into 1/M and 1/(M+1). The program counter 25 divides a clock signal divided by the prescaler 24 into 1/N. The swallow counter 26 divides a clock signal divided by the prescaler 24 into 1/A. The controller 27 outputs a mode control signal MC for controlling the prescaler 24 by using output signals from the swallow counter 26 and the program counter 25.
The output frequency fvco of the output clock signal ICLK from the VCO 23 is divided by the dual modulus prescaler 24 having division ratios 1/M and 1/(M+1), and then the divided frequency is inputted into the program counter 25 and the swallow counter 26.
The swallow counter 26 is used for selecting division ratios of the prescaler 24.
The prescaler 24 is set at a division ratio 1/(M+1) until the swallow counter 26 counts A pulses.
After the swallow counter 26 counts A pulses, the prescaler 24 is set at a division ratio 1/M. The time of A/N is a division ratio of 1/[(M+1)×N], and the time of (N−A)/N is a division ratio of 1/M×N.
Here, the comparison frequency fp is defined by the following equation 5:                                                         fp              =                            ⁢                              fvco                                  {                                                            (                                                                        (                                                                                    (                                                              M                                +                                1                                                            )                                                        ×                            N                                                    )                                                ×                                                  A                          N                                                                    )                                        +                                          (                                                                        (                                                      M                            ×                            N                                                    )                                                ×                                                                              (                                                          N                              -                              A                                                        )                                                    N                                                                    )                                                        }                                                                                                        =                            ⁢                              fvco                                  {                                                            (                                                                        (                                                      M                            +                            1                                                    )                                                ×                        A                                            )                                        +                                          (                                                                        (                                                      N                            -                            A                                                    )                                                ×                        M                                            )                                                        }                                                                                        Equation        ⁢                                   ⁢        5            
Accordingly, the output frequency fvco is defined by the following equation 6:                                                         fvco              =                              fp                ⁢                                  {                                                            (                                                                        (                                                      M                            +                            1                                                    )                                                ×                        A                                            )                                        +                                          (                                                                        (                                                      N                            -                            A                                                    )                                                ×                        M                                            )                                                        }                                                                                                        =                              fp                ⁡                                  (                                      A                    +                                          M                      ×                      N                                                        )                                                                                                        =                              fr                ⁡                                  (                                      A                    +                                          M                      ×                      N                                                        )                                                                                        Equation        ⁢                                   ⁢        6            
In Equation 6, N is the coefficient of M, but it is not the coefficient of A. As a result, if the value of A varies, the reference frequency fr is changed. In this way, if the prescaler 24 is used in the PLL, the channel separation can be the reference frequency fr. Particularly, a pulse swallow is used because the prescaler 24 can be set at a high division ratio in a high-frequency synthesizer.
Generally, the output frequency fvco is defined by the following equation 7:                     fvco        =                              {                                          (                                  M                  ×                  N                                )                            +              A                        }                    ×                      fosc            R                                              Equation        ⁢                                   ⁢        7            
Here, M is the division ratio of the prescaler 24, and N is the set point of the program counter 25. A is the set point of the swallow counter 26, having a relation of A<N. In Equation 7, fosc represents the reference oscillating frequency, and R represents the set point of the reference counter.
However, the VCO of the above-described conventional PLLs cannot be used in various frequency bandwidths due to its non-linear characteristic.